1. Field of the Invention
This invention relates to a phase-locked loop circuit which extracts a clock signal out of a received signal obtained from a token ring network using a differential Manchester code or from various local area networks (LAN) using Manchester code. In particular, this invention relates to a phase-locked loop circuit which is capable of extracting a clock signal out of a received signal having any data pattern at a stable follow-up speed, and smoothly recovering to a synchronous state without causing a bit slip even in the case where a center edge is lost. This invention also relates to a phase-looked loop circuit which is capable of detecting a period in which no received signal is found, thus evading a big shift of the synchronizing frequency of this phase-locked loop circuit, the shift which arises within said period, and thus quickly recovering to said synchronous state once a received signal is again found.
2. Description of Prior Arts
A prior art phase-locked loop circuit (referred to as PLL, below) includes a phase comparator 51, a charge pump 53, and a voltage controlled oscillator (referred to as VCO, below) 55, as shown in FIG. 14.
In this circuit arrangement, phase comparator 51 detects the phase difference between a received data signal "DATA" and a clock signal "Clock" generated by VCO 55. A current having a magnitude corresponding to the phase difference detected by comparator 51 is applied to charge pump 53 so as to change the control voltage for VCO 55. When the phase of clock signal "Clock" is behind that of data signal "DATA", charge pump 53 is operated to increase the oscillating frequency of VCO 55, so that VCO 55 catches up to the data signal.
Manchester code is a modulation system in which an information signal and clock signal "Clock" are combined into received signal "DATA". This code has two modes, one of which has two edges in one bit time and the other has only one edge.
FIG. 2a shows how Manchester code is synthesized from data signal "DATA" and clock signal "Clock". In order to produce a differential Manchester code, differential-encoding is applied first to the data, and then, the resulting data signal is converted into Manchester code. Therefore, both codes basically have the same characteristics with each other. Phase information required by a PLL is taken from the respective edge positions of a data signal. In Manchester code, the edge frequency varies depending on the data pattern of a received data signal.
In the prior art PLL shown in FIG. 15, a phase comparison is carried out so as to drive charge pump 53 only when a rising edge is detected. In this case, however, the edge generation rate is not constant. Thus, the generating position of edges cannot be predicted. In this circuit, therefore, charge pump 53 is driven after having detected a rising edge in a received signal.
FIG. 16 is a timing chart for explaining the operation of the circuit shown in FIG. 15. Flip flop Q10 detects the rising edge of data signal "DATA". Flip flop Q11 detects the rising edge of clock signal 2CLK which is obtained from VCO 55 and has a frequency two times as high as that of the clock component in the received data signal. From the time when flip flop Q10 detects the rising edge of data signal "DATA" to the time when flip flop Q11 detects the rising edge of clock signal 2CLK, current source I10 supplies charge pump 53 with charging pulses. While clock signal 2CLK is in an active state, flip flop Q11 keeps its set state, and therefore, flip flop Q10 is reset by this set signal. Then, operation switch SW10 is turned off to stop the generation of charging pulse. During the set state of flip flop Q11, current source I11 generates discharging pulses. Once clock signal 2CLK comes into an in-active state, flip flop Q11 is reset by flip flop Q10, thus making switch SW11, which has been operated to generate discharging pulses, off.
As is evident from the first pulse of received data signal "DATA" shown in FIG. 16, when no phase difference exists between data signal "DATA" and clock signal 2CLK, a balance is kept between the charging and discharging pulses. Therefore, the amount of resulting charge in the charge pump does not vary at the end of an operation. And thus, the control voltage for VCO 55 does not vary. On the other hand, if the phase of data signal "DATA" precedes that of clock signal 2CLK, the charging pulses are generated longer in time, thus increasing the amount of stored charge in charge pump 53. The control voltage for VCO 55 becomes higher so as to increase the oscillating frequency. Thus, the phase delay in the clock signal will be recovered. On the contrary, when the phase of clock signal 2CLK precedes that of the data signal, the control voltage for VCO 55 becomes lower in magnitude, thus decreasing the oscillating frequency.
In the prior art PLL as explained above, phase comparator 51 detects the time difference between the rising edge positions of data signal "DATA" and clock signal 2CLK from VCO 55. According to the detected result, comparator 51 outputs pulse signals for switching the current sources which supply charge pump 53 with a charging or discharging current.
As explained above, in said PLL, a pair of charging and discharging pulses are always generated at every phase comparison. Thus, a triangular pulse component is always included in the control voltage for VCO 55. This component is disadvantageous because it unstabilizes the VCO 55 operation.
In addition, the frequency of phase comparison varies due to the differences in data patterns. Thus, the follow-up speed of a PLL circuit varies due to the differences in data patterns.
Still in addition, in a token ring communication system, signals are sometimes not sent on the ring for a certain period when a node is added onto the ring. At this moment or the after, in order to recover to the synchronous state, the follow-up operation of the PLL should be carried out smoothly. In the prior art PLL, however, the lack of center edge is continuously detected during said period in which no received signal is sent. In this case, the charge pump repeats the operation for compensating the lack of center edge. Therefore, the accumulated voltage in a loop filter connected to the charge pump gradually varies. As a result, when a received signal is found again, it is difficult for the PLL to smoothly recover to the original synchronous state.